Temp 4 temperature sensor in the ESS was shorting out the ESS DAQ so it has been removed. Both the temperature sensor on the batteries and the 5V/Gnd wires from the ESS DAQ were removed.
James found a flaw in the old version. We updated it, it’s much more complicated, but it’s right this time (hopefully)
The LPRDS SCADA Website is now online with database access. You can check the error, fault, and system state logs, as well as see data from the database for each device. The site is accessible only from computers on AEC 4th floor.
Incorporate GNUPlot for data plotting
– Incorporate Sunny Boy
System status page
– GNUPlot fully incorporated into data access page
– System status page show important current sys. info
– Expanded data/log selection capabilities from by day to by hour
Updated SC algorithm state diagram–transition from S4 to S2 should never happen. If V <= 20%, this is an undersupply fault and S4 transitions to SF.
Lists of requirements we’ve chosen not to meet (ReqNOTMet) and Requirements that do not need to be tested (ReqNOTTested) have not been changed.
Examples: requirements not met include things like per-cell mgmt; requirements that we don’t have to test include things like the FIT PC runs Linux
Everything else is tested, analyzed, or inspected in either the subsystem QA reports or in the ATP.
New ATP Draft: ATP (04-27)
New List of Requirements Not Met: ReqNOTMet
New List of Requirements that we don’t need to test for: ReqNOTTested
60 Hz has been achieved within the specification of +- .05%. This was done by using the oscilloscope, and signal generator. The signal generator was set at 60Hz, and the sync output was used to hold it at the same place on the scope. The output from the inverter moved in relation to the output from the signal generator. We measured the time between when the two seemed to be in phase, and from this we were able to get the difference in frequency. The signal generator has an accuracy of 100ppm worst case, making our margin that we needed to measure a little smaller. Through tweaking the DDS increment, we were able to get the waveforms to have a time of 200s, which corresponds to .005Hz, well within the .03Hz required. Even with the 100ppm error of the scope, this is still within the specification put forth in the statement of work.
Below is the output of the scope at the conclusion of the test.
This is our first sine wave out of the inverter, using our filter. It is a little squashed at the top and bottom of the cycle due to saturating the PWM.
After some tweaking of the code for PWM, we got a cleaner sine wave out. It is about 60Hz, but we need to test to make sure it is within our requirement of .05%