This app illustrates the problem formulation for VLSI Floorplanning, in which interconnected modules of different sizes and shapes are assigned to positions on a layout surface to form a placement. Connections are specified as nets between terminals on different modules.
The quality of placement is usually estimated using a weighted sum of cost estimates. Area is estimated as the area of the bounding box containing all modules. Wirelength can be estimated in a number of ways, but a common approach (used here) is to compute half the perimeter of the bounding box that contains the terminals of a net. Module overlap is often included in a cost function as a penalty function (these are often used in iterative algorithms like simulated annealing). Finally, congestion estimates the wireability of interconnect regions between placed modules.
If you’re interested, here is the source code
The main files are in placement/apps
The app displays modules as yellow rectangles; terminals are marked by small black rectangles. Connections between modules are displayed using red lines. This display of nets is sometimes known as a “rat’s nest” diagram. Cost estimates are shown above the placement display. Note that congestion estimates are not included (yet).
The app allows the user to manipulate a floorplan placement using the mouse – just click on a module and drag it. Modules can also be transformed in the following ways:
- Rotate – click the mouse over a module.
- Flip Horizontal – shift-click mouse over a module
- Flip Vertical – alt-click mouse over a module
For more information about Placement, see a VLSI CAD textbook such as M. Sarrafzadeh and C. K. Wong, An Introduction to VLSI Design, McGraw-Hill, 1996.